The present invention relates to a liquid crystal display apparatus, and, more particularly, to a liquid crystal display apparatus of the high resolution active matrix type.
Since an active matrix liquid crystal display apparatus can display images with a high contrast, and also has a low profile and is light in weight, it has been widely used for portable note-type computers and portable image display apparatuses. For example, this type of display apparatus is reported on pages 879 to 881 in the SAID International Symposium Digest of Technical Papers. A detailed description of the active matrix drive method and liquid display modules is found in xe2x80x9cLiquid Display Technologiesxe2x80x9d, Sangyo Tosho Publishing Co., authored and edited by Shouichi Matsumoto.
In order to provide an understanding of the difference between conventional devices and the present invention, a conventional display apparatus, as shown in FIG. 17, and the liquid crystal display apparatus of the present invention, as shown in FIG. 1, will be outlined below.
FIG. 1 is a schematic diagram of the present invention, in which the display areas 6, 7 are composed of a plurality of pixels 1, each arranged at a respective intersection between the main scan wiring lines 12 and the signal wiring lines 11, which are arranged in a matrix wiring configuration, and sub scan wiring lines 19 are arranged in the same direction as the signal wiring lines 11. In order to drive those wiring lines, a main scan circuit 10, a sub scan circuit 15, a signal circuit 9 and a control circuit 13 for controlling the control signals are provided, along with an opposed electrode 17 formed on the opposite substrate which faces the pixels and supports the liquid crystal. The electric power for driving this display apparatus, the synchronous signals and the display data are applied thorough a flexible wiring strip 14.
For driving an individual pixel, a couple of TFT""s are connected between the drain wiring and the display electrode 2 and in series with the main circuit of the TFT, and the individual gate electrodes of the TFT""s are connected to the main scan wiring lines and the sub scan wiring lines. A single main scan wiring line 12 is assigned to every two pixels of a column, and it is connected in common to the gate terminals of dual TFT""s 3 for the main scan wiring. TFT""s 4 for the sub scan wiring are arranged in a repetitive sequence of nch, pch, nch and pch in every column, and their gate terminals are connected to identical sub scan wiring lines in the row direction, and those lines are connected to one another outside the matrix, so that the TFT""s are driven all together by the sub scan circuit 15. In addition, a retention capacitance 5 is arranged at the display electrode, and one terminal of the retention capacitance is connected to the display electrode, and its other terminal is connected to the terminal of an adjacent retention capacitance and is connected to the common electrode power supply circuit located outside the matrix.
In order to drive this matrix using a linear serial method, the following drive scheme is employed. At first, in order to select the pixels for every column, every two columns of TFT""s 3 for the main scan wiring are turned on and two columns of pixels are selected by applying the main scan pulse to the main scan wiring; and then, the TFT for the sub scan wiring among the selected pixels in two columns is alternately turned on by setting the voltage of the sub scan wiring to logic level H for almost a half period of the main scan pulse and by setting logic level L for the remaining half period. The pixels arranged in a single column in which both the TFT 3 for the main scan wiring and the TFT 4 for the sub scan wiring are simultaneously turned on can be selected.
In the display apparatus with a conventional structure, as shown in FIG. 17, the pixel TFT 102 is arranged at the intersection of the scan wiring line 100 and the signal wiring line 101, with the main circuit of the TFT being connected between the signal wiring line 101 and the display electrode 103 and the scan wiring line 100 being connected to the gate electrode of the TFT. In this case, the number of scan wiring lines is required to be equal to the number of pixels arranged in the column direction. As the selection pulse is applied sequentially to the scan wiring line from the first column, the pixel of the first column is selected by turning on the pixel TFT of the first column and the liquid crystal capacitance composed of the display electrode 104 and the opposed electrode 105 is charged by the signal voltage of the signal wiring line 101; and then, the pixel TFT of the first column is turned off, and next, the second and remaining columns are repetitively driven so as to be selected, until all the scan wiring lines are scanned, and the display operation is completed by applying a designated signal voltage to all the pixels.
In an attempt to provide a panel that is configured with a higher resolution in the conventional technology, the selection time, that is, the gate time for a single pixel is reduced because the number of the scan wiring lines increases. Thus, a speeding up of the response in the scan wiring is required. However, as the number of pixels for a single column inevitably increases for attaining the higher resolution, the wiring time constant represented by the product of the wiring resistance and the wiring capacitance increases and the transition response time at the terminal of the wiring increases. In attempting to speed up the transient response, though there may be an alternative way in which the wiring resistance is made smaller, a modification of the process is required, which is not feasible realistically. In addition, though there may be an alternative way in which the wiring width is made larger in order to reduce the wiring resistance, this results in a decrease in the numerical aperture of the pixel part and an increase in the electric power consumption of the panel itself.
The present invention is characterized in that, by combining the main scan pulse generated by the main scan wiring lines arranged in the row direction and the sub scan pulse generated by the sub scan wiring lines arranged in the column direction along the signal wiring lines, a pixel line is selected by a TFT circuit formed at the pixel part. By applying a pulse having a time width twice as long as the selection time for the individual column to the main scan wiring lines having a long wiring delay time, and by applying a high-speed sub scan pulse to the sub scan wiring lines having a wiring length in the row direction, a single row can be selected. With this configuration, the pulse width of the wiring selection pulse can be extended to be twice as long as that in the prior art even in a panel with high definition, and an excellent display image can be obtained even if the wiring response time may increase.
In accordance with the present invention, if the number of sub scan wiring lines is defined to be xe2x80x9caxe2x80x9d, the selection time width of the main scan wiring can be extended xe2x80x9c2axe2x80x9d times, and the main scan wiring pulse width can be extended four times, eight times or sixteen times by making the number of the sub scan wiring lines two, three or four, which leads to an advantageous aspect for making it easier to form a high-definition panel.
In addition, according to the present invention, the extension of the main scan wiring pulse width may contribute advantageously to the reduction of the frequency and energy of the unnecessary radiation generated from the main scan wiring.
And, furthermore, by applying this drive method to a reflection liquid crystal display apparatus, a high-definition and low electric power consumption panel can be advantageously provided.
As for the method in which plural TFT""s for pixel selection are formed in a pixel, there is a case as disclosed in Japanese Patent Application Laid-Open No. 9-329807 (1997). A couple of TFT""s are connected between the display electrode and the signal wiring line by connecting the main circuit of the TFT""s in series and arranged in a single pixel, and its gate terminals are connected to a scan wiring line and a block selection signal wiring line, respectively. However, with this arrangement, the scan wiring line is extracted for an individual column and the width of the scan pulse is identical to that in the prior art described above. In addition, a pixel is selected by a unit for the block defined in the horizontal direction, in which its expected effect is to reduce the electric power consumption for driving the display panel for animation display without driving the pixel which does not require data writing, and thus, its structure and effect is completely different from that of the present invention.
In order to make the characteristic of the present invention clear, the time relation with respect to the drive condition of the scan wiring in the prior art will be described below. The frame frequency corresponding to the period while scanning the whole display panel is defined to be 60 Hz or higher. This frequency is required for reducing the flicker on the display panel. The relation between the frame time and the selection time for a single scan wiring line is given by the following approximate equation.
Tg=1 (fxc3x97N),
in which Tg is the selection time for the single scan wiring line, f is a frame frequency and N is the number of the scan wiring lines. The minimum frame frequency is 60 Hz, and N represents the definition of the panel which is often 480, 600 or 768 for a note-type computer, and is often 1024 or 1200 for a large-sized panel such as used for a desk-top computer. The selection time decreases reciprocally as N increases. For example, Tg is 30 xcexcsec for N=480, and Tg is 14 xcexcsec for N=1200. As the number of the scan wiring lines increases, the number of pixels in the horizontal direction in the pixel area, that is, the number of rows in the display matrix increases in proportion to the number of scan wiring lines. As the aspect ratio of the display area is 3 to 4 in the display apparatus to be used for a personal computer, the pixel structure in terms of pixels in the horizontal direction by pixels in the vertical direction is from 640 pixelsxc3x97480 pixels to 1600 pixelsxc3x971200 pixels.
As described above, in the conventional liquid crystal display apparatus, as the number of pixels connected to a single scan wiring line inevitably increases in response to provide the display matrix with a high resolution, the wiring capacitance increases and the transient response time of the main scan wiring increases. In contrast, there is a conflict in that the selection time for a single pixel becomes shorter, and the response of the main scan wiring line should be improved for speeding up the operation.
In the recent trend in multimedia technologies, a high resolution display capability for the display apparatus used in personal computers is an indispensable requirement, and high resolution compliance is an important goal to be achieved.
An object of the present invention is to provide a liquid crystal display apparatus that enables high-definition display images without decreasing the selection time of the main scan time, even if the pixel part is configured to provide a high resolution.
Another object of the present invention is to provide a liquid crystal display apparatus in which, by making the time width of the scan pulse larger, a high display quality can be obtained even if the output resistance of the main scan circuit for driving the main scan wiring is high and the drive performance is low, and in which the transistor area of the output stage can be reduced and the circuit width can be reduced.
Another object of the present invention is also to provide a liquid crystal display apparatus in which, by making the selection time of the main scan wiring and the signal wiring longer, the output accuracy of the signal circuit is improved and a high resolution display can be established with higher accuracy in the gradation sequence.
In order to attain the above objects, in accordance with the present invention, a couple of TFT""s are connected to the signal wiring line and the display electrode by connecting the main circuit of the TFT""s in a series connection, one of the gate electrodes of two TFT""s is connected to the main scan wiring line formed as one line for every two pixels, and the other of the gate electrodes of two TFT""s are connected to the sub scan wiring line formed as one line for every single signal wiring line, and the main scan wiring line is driven with a scan pulse having a width that is twice as long as the width of the selection time for a single column by the single main scan wiring line formed for every two columns and a single sub scan wiring line, which leads to an excellent display quality.
In order to attain another object, in accordance with the present invention, three TFT""s are connected to the signal wiring line and the display electrode by connecting the main circuit of the TFT""s in a series connection. A single main scan wiring line is assigned to four columns of pixels, in which the polarity of the pixel TFT is defined by a repetitive and cyclic use of patterns, Nch-Nch-Nch, Nch-Nch-Pch, Nch-Pch-Nch and Nch-Pch-Pch. Each Nch device at the gate electrodes of the first one of the three TFT""s is connected in common to the main scan wiring line. For the other two TFT""S, the second ones have their gate electrodes connected to each other and the third ones have their gate electrodes connected to each other, then each is connected individually to two sub scan wiring lines. With this configuration, the voltage relation of two sub scan wiring lines for four columns of pixels connected to a single man scan wiring lines produces four states, H-H, H-L, L-H and L-L, and one of the columns among them can be selected sequentially. In this case, even if the main scan wiring line is driven with a scan pulse having a width four times longer than the width of the selection time for a single column, an excellent display quality can be obtained.
In order to attain another object, in accordance with the present invention, a couple of signal wiring lines are formed for an individual row, and two columns are selected at one time and operated for writing. As the scan pulse width is eight times longer than the width of the selection time for a single column, and the writing time for the signal voltage can be spent twice, the accuracy in writing the signal voltage can be increased and the display quality can be increased to a large extent.